(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a high performance metal oxide semiconductor field effect transistor (MOSFET), device, via the implementation of a disposable insulator spacer component and of a raised source/drain region.
(2) Description of Prior Art
Advances in specific semiconductor fabrication disciplines such as photolithography and dry etching, have allowed the attainment of sub-micron MOSFET devices to be routinely achieved. In addition to the breakthroughs in the above fabrication disciplines, process and structural innovations have also contributed to the attainment of MOSFET devices comprised with sub-50 nm channel lengths. To successfully form sub-50 nm MOSFET devices specific regions, such as source/drain regions have to be shallow. However it is difficult to maintain shallow source/drain regions during subsequent silicide procedures used to reduce source/drain resistance. The thicker the silicide formation the greater the consumption of source/drain region, therefore presenting process difficulties when attempting to form silicide on the shallow source/drain regions needed for sub-50 nm MOSFET devices. One method used to overcome the vulnerability of shallow source/drain regions in a semiconductor substrate, during silicide formation, is the raised or elevated source/drain structure, formed via selective growth of single crystalline silicon on the shallow source/drain region. The selectively grown raised source/drain structure, comprised with the same dopant conductivity type as the underlying shallow source/drain region in the semiconductor substrate, can easily except overlying silicide formation without consumption of the underlying shallow source/drain region located in a top portion of the semiconductor substrate. The procedures used to form raised source/drain structure incorporates removal of an insulator spacer located on the sides of a gate structure to expose additional portions of a heavily doped source/drain region, and therefore when overlaid with the raised source/drain structures provide still additional decreases in source/drain resistance. The removal of the insulator spacer component can however damage the exposed shallow source/drain region. In addition some raised source/drain fabrication procedures do not allow silicide formation to occur on the gate structure, therefore limiting gate resistance reduction.
The present invention will describe a novel process sequence in which a raised source/drain structure is formed via low temperature selective epitaxial growth procedures after formation of the shallow source/drain region in the semiconductor substrate, and after removal of an overlying or outer insulator spacer component, therefore regrowing non-damaged silicon on the possibly damaged surface of the shallow source/drain region. In addition a novel process sequence for etching back a horizontal segment of an underlying, or inner insulator spacer component, allowing a portion of a lightly doped source/drain (LDD), region to be exposed and overlaid by the subsequently grown raised source/drain structure, is also presented in this invention. Prior art such as Moslehi, in U.S. Pat. No. 5,949,105, Moslehi, in U.S. Pat. No. 5,496,750, Michael et al, in U.S. Pat. No. 6,197,645 B1, Hu et al, in U.S. Pat. No. 6,287,926 B1, Kawai et al, in U.S. Pat. No. 5,296,727, and Chau et al, in U.S. Pat. No. 5,434,093 B1, describe methods of forming raised source/drain structures and methods to remove disposable spacers. However none of these prior art describe the novel process sequence provided in this present invention in which an elevated source/drain structure is formed on a shallow source/drain region and on a portion of a lightly doped source/drain region.